1. Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells with page erase and negative voltage gate erase. More particularly, the present invention relates to an improved negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure.
2. Description of the Prior Art
In U.S. Pat. No. 5,077,691 to Sameer S. Haddad et al, issued on Dec. 31, 1991, there is disclosed a flash EEPROM array which has a negative gate voltage erase operation. The '691 patent is assigned to the same assignee as in the present invention and is hereby incorporated by reference. One of the advantages obtained by applying a negative erase voltage through the word-lines to the control gates rather than applying a positive erase voltage through the source common line to the source regions of all memory cells in the flash EEPROM array simultaneously is that erasure can be made to occur selectively on a row-by-row basis rather than by having to erase all the memory cells of a chip simultaneously. Preferably, groups of rows are formed such that each group defining a sector provides a page-selectable erase block. For example, the memory array consisting of a large number, N.times.M (i.e., 1,000 or more) of such memory cells are typically formed on a single integrated circuit chip in an N.times.M matrix form, where N equals the number of columns and M equals the number of rows. If the matrix is assumed to have 1 million cells (i.e , 1024.times.1024), then groups of 128 rows each could be formed together so as to divide the matrix into eight sectors. Hence, the memory array could be erased selectively sector-by-sector or any given number of sectors rather than all memory cells being erased simultaneously.
During a sector-erase mode of operation, a relatively high negative potential (i.e., -12 V) is applied to the control gates via the wordlines of the selected sector(s) while VCC volts is applied to the control gates of memory cells in the non-selected sectors. Further, the source regions of all transistors in the selected sector are raised to a positive level of approximately +0.5 V to +5.0 V, and the drain regions thereof are allowed to float. In FIG. 4 of the '691 patent, there is shown a schematic circuit diagram of a single stage used for forming a negative charge circuit of FIG. 4C containing five such stages in order to generate the high level negative potential of approximately -13 V to -15 V. The negative charge pump circuit of FIG. 4C is used for the charge pump block 204 shown in FIG. 2B of the '691 patent. Each charge pump stage is formed of a pair of capacitors and a pair of P-channel transistor devices. Since the P-channel transistor devices have such a large body effect coefficient and the back-bias is so high, the threshold voltage V.sub..phi. 's can be as high as -2.5 volts. As a result, the five-stage charge pump circuit of FIG. 4C is thus made impractical.
In U.S. Pat. No. 5,126,808 to Antonio J. Montalvo et al. issued on Jun. 30, 1992, there is taught a flash EEPROM array with paged erase architecture. The '808 patent is also assigned to the same assignee as in the present invention and is hereby incorporated by reference. In FIG. 7A of the '808 patent, there is shown a schematic circuit diagram of a single stage of a charge pump circuit, similar to FIG. 4 of the '691 patent, for generating the negative gate erase voltage. FIG. 7B depicts five such charge pump stages connected together to form the charge pump circuit for generating the -13 V. Again, the construction of each charge pump stage is done with a pair of capacitors and a pair of P-channel transistors.
The present invention represents a significant improvement over the charge pump circuits shown in the respective '691 and '808 patents discussed above. The negative power supply of the present invention is used for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure. The negative power supply includes a negative charge pump circuit formed of a plurality of charge pump stages for generating a high negative voltage and a cancellation circuit coupled to the charge pump circuit for effectively canceling out threshold voltage drops in the charge pump circuit. The negative power supply further includes a regulation circuit which is responsive to the high negative voltage and a reference potential for generating the regulated negative potential to be independent of a power supply potential VCC.